Integrated circuits and other semiconductor devices are prevalent in all aspects of today's world. The integrated circuits or other semiconductor devices are formed on tiny substrates which are typically made of semiconductor materials and are called chips. Many components that are conventionally considered to be electronic components, and various other products in today's marketplace, utilize one or several chips, i.e. they utilize one or several integrated circuits or other semiconductor devices, which will hereinafter be referred to collectively as integrated circuits. Each integrated circuit includes a unique design.
The design of each integrated circuit is a painstakingly detailed process of selecting, positioning, combining and interconnecting various active and other components to form the integrated circuit. The design procedure includes producing a circuit schematic, i.e. a circuit diagram of the integrated circuit, testing the circuit schematic and simulating operation of the integrated circuit using a netlist of the circuit schematic.
The chips are formed of multiple material layers and include various active devices such as transistors and many other devices such as resistors, capacitors and the like. These devices are formed using one or more material layers formed over the substrate used for the chip, and the substrate itself. Intricate patterning techniques are used to pattern each of several material layers to form the various components and interconnect them through dielectric materials. In order to form an integrated circuit on a chip, a layout of each of several different device layers must be generated from the schematic of the electrical circuit diagram.
Prior to carrying out any fabrication operation to manufacture the chip, both the electronic circuit diagram, i.e. schematic, and the device layout must be tested. More particularly, both a netlist of the circuit diagram and a netlist representative of the layout database, must be tested.
The circuit schematic must be also compared to the layout. LVS, “Layout Versus Schematic,” is a type of electronic design automation (“EDA”) verification that determines whether a particular integrated circuit layout corresponds to the schematic or circuit diagram of the design. LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, and vice versa, as well as the connections between the components. This netlist that represents the drawn shapes of the layout that represent electrical components is compared by the LVS software against a netlist of the schematic or circuit diagram.
The operation and performance of the manufactured chip often depends on artifacts of the layout that are not present in the circuit schematic. Parasitic effects such as parasitic capacitance, parasitic inductance and parasitic resistance come into play and affect circuit operation and performance. These and other parasitic effects are due to the arrangement and proximity of components and interconnect features in the three-dimensional circuit produced. Such effects must be taken into account in simulating operation of the circuit prior to manufacture.
In current design methods, one circuit schematic without parasitic components is maintained and used to generate a layout and is used in the LVS check. A separate circuit schematic with a pre-estimate of parasitic components is maintained and used to test for estimated parasitic capacitance, parasitic inductance and parasitic resistance.